(1) Field of the Invention
The present invention relates to a method for making metal capacitors for integrated circuits, and more particularly relates to a method for making metal-insulator-metal (MIM) capacitor structures compatible with copper metallization schemes for wiring-up CMOS circuits. The MIM capacitors utilize the pad protect layer with copper (Cu) bottom electrodes and aluminum/copper (Al/Cu) top electrodes to achieve high capacitance per unit area while providing low series resistance resulting in a circuit having capacitors with high figure of merit Q.
(2) Description of the Prior Art
Capacitors on semiconductor chips are used for various integrated circuit applications. For example, these on-chip MIM capacitors can be used for mixed signal (analog/digital circuits) applications and radio frequency (RF) circuits. These capacitors can also serve as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution.
Typically these capacitors are integrated into the semiconductor circuit hen the semiconductor devices are formed on the substrate. For example, the one or two doped patterned polysilicon layers used to make the field effect transistors (FETS) and/or bipolar transistors can also be used to form the capacitors. Alternatively, the capacitors can be fabricated using the multilevels of interconnecting metal patterns (e.g., Al/Cu) used to wire up the individual semiconductor devices (FETs).
In recent y a portions of the AlCu metallization have been replaced with copper (Cu) to significantly reduce the resistivity of the conductive metal lines and thereby improve the RC (resistancexc3x97capacitance) delay time and improve circuit performance.
Generally the capacitors can be integrated into the circuit with few additional process steps. The capacitance C for the capacitor is given by the expression
C=⊕A/d
where ⊕ is the dielectric constant, A is the capacitor area, and d is the thickness of the capacitor dielectric layer between the two capacitor electrodes. Typically the figure of merit Q for a capacitor in a circuit is Xc/R, where Xc is the capacitor reactance expressed in ohms, and R is the resistance (ohms) in series with the capacitance reactance. To improve the figure of merit it is desirable to maximize Xc while minimizing the R. In conventional capacitor structures multiple contacts are made to the relatively thin capacitor top metal (CTM) electrode to minimize resistance and improve the figure of merit Q. This is best understood with reference to FIG. 1. As shown in FIG. 1, when a more conventional MIM capacitor C is formed on the partially completed CMOS substrate 10, the CBM electrode is formed from an upper interconnecting metallurgy layer 15 of TiN/AlCu/TiN. An interelectrode dielectric layer 17 is formed on the CBM electrode top surface. A capacitor top metal (CTM) electrode is formed from a patterned relatively thin AlCu/TiN layer 19, and a planar insulating layer 21 is formed over the capacitor to insulate the capacitor and provide support for the next level of metal interconnections 25. A TiN/AlCu/TiN layer is then deposited and patterned to form the next level of metal interconnections. Vias (holes) 23 are etched in the insulating layer 21 to make contact to the CBM electrode 15 and the CTM electrode 19.
Unfortunately, to minimize the series resistance R to the capacitor it is necessary to etch a series of closely spaced vias 23. For example, U.S. Pat. No. 5,926,359 to Greco et al., and U.S. Pat. No. 5,906,567, to Wang et al. are similar to the capacitor structure depicted above. In U.S. Pat. No. 5,406,447 to Miyazaki, a method is described for making an MOS, MIS, or MIM capacitor incorporating a high-dielectric material, such as tantalum oxide, strontium nitrate and the like, as the interelectrods dielectric layer. In U.S. Pat. No. 5,812,36 to Oku et al., a method in described for making a compatible MIM capacitor on a gallium arsenide substrate, but does not address the method of making MIM capacitors integrated with copper metallization schemes for CMOS devices on silicon substrates.
There is still a need in the semiconductor industry to for metal-insulator-metal (MIM) capacitors with high capacitance and low series resistance for improved figure of merit Q for advanced Cu metallization schemes on integrated circuits.
A principal object of the present invention is to fabricate a Metal-Insulator-Metal (MIM) capacitor structure having a high figure of merit Q for improved circuit performance using CMOS technology.
A second object of this invention is to provide this improved capacitor using a Cu damascene process to form the Capacitor Bottom Metal (CBM) and using a patterned pad protection layer for the Capacitor Top Metal (CTM), which is also patterned to form a level of metal interconnections and to protect the pad contacts.
A third object of this invention is to use an insulating protecting buffer layer, which is used to protect the Cu CBM layer from reacting with the SiO2 interelectrode dielectric layer for the MIM capacitor, that also serves as a portion of the interelectrode dielectric layer.
A further object of the present invention by a second embodiment is another method of fabricating a Metal-Insulator-Metal (MIM) capacitor having a high figure of merit Q requiring no additional masks or metal layers.
In accordance with the objects of the present invention, a method is described for making MIM capacitors having high figure of merit Q by reducing the series resistance associated with the capacitor. The method is compatible with the copper damascene process for CMOS circuits having planar surfaces formed by chemical/mechanical polishing (CMP).
The method for making MIM capacitors for CMOS circuits begins by providing a semiconductor substrate having partially completed CMOS circuits including several levels of electrical interconnections. The next level of metal interconnections is formed by the damascene process, which involves depositing a first insulating layer, for example a chemical-vapor-deposited (CVD) SiO2, and etching recesses for CBM electrodes, pad contacts, and the next level of metal interconnections. Typically for the damascene process, a barrier layer is deposited on the first insulating layer, and a Cu layer is deposited by either physical vapor deposition (PVD) or by electroplating. The Cu layer is then polished back to form the CBM electrodes, the pad contacts and interconnections in the recesses. Next an insulating protecting buffer layer is deposited. This buffer layer prevents the underlying Cu layer from direct contact with the SiO2 layer (the interdielectric layer) that would cause Cu corrosion. Then a second insulating layer, for example SiO2, is deposited on the insulating protecting buffer layer to serve as a portion of a capacitor interelectrode dielectric layer. Alternatively, if the capacitor interelectrode dielectric layer is silicon nitride (Si3N4), then the insulating protecting buffer layer is not required.
Continuing with the process, a conducting metal protect buffer layer, such as TiN, TaN, Ta, or Ti is deposited to protect the second insulating layer during the photoresist processing. A first photoresist layer is deposited. A pad contact mask is used to expose and develop the first photoresist, and plasma etching is used to etch pad contact openings (windows) and interconnect contact openings in the metal protect buffer layer and the second insulating layer to the insulating protecting buffer layer. The remaining first photoresist layer is then removed. Next the insulating protecting buffer layer in the contact openings is removed to the underlying Cu layer, and a blanket pad protection metal layer is deposited. The pad protection metal layer, which is preferably TaN/Al/TaN or TaN/AlCu/TaN, protects the Cu from corrosion and also serves as the next level of interconnections. A second photoresist mask and plasma etching are used to pattern the blanket pad protection metal layer to form pad protection over the pads, and to also form capacitor top metal (CTM) electrodes, and to form the next level of interconnecting lines. A passivating third insulating layer, such as PECVD silicon nitride and high density plasma (HDP) oxide is deposited to protect the underlying patterned metallurgy. A third photoresist layer is deposited and is exposed through the pad contact mask and developed to provide openings. The third photoresist mask is now used to plasma etch openings through the passivating third insulating layer to the pad protection over the pads and to the CTM electrodes. The remaining third photoresist layer is then removed to complete the MIM capacitor integrated with the CMOS circuit.
In a second embodiment the process is similar to the first embodiment up to and including the formation of the interelectrode dielectric layer. In this second embodiment pad contact openings and vias are etched in the insulating protecting buffer layer and the second insulating layer. The pad contact openings are etched to the Cu pad contacts, and the vias are etched for the electrical interconnections. The next level of metal, consisting of TiN/AlCu/TiN, is deposited and patterned to form the next level of metal interconnections and concurrently form the capacitor top metal (CTM) electrodes. This results in a relatively thick CTM electrode having low series resistance and a low-series-resistance Cu CBM electrode that provides a higher figure of merit Q (Xc/R). The remaining process steps are similar to the first embodiment. A passivation layer is deposited and openings are etched for the pad contacts.